More power is a good thing when you’re talking desktops, but for notebooks, more power means less battery life – and in this age of Ultrabooks and ultraportables, that just isn’t acceptable to a lot of manufacturers. In yet another step towards making those Ultrabooks ultra long lasting, the SATA-IO organization announced a new feature yesterday: SATA DevSleep. Basically, DevSleep lets PHY and other circuitry drop into an almost completely powerless state – rather than a still power-consuming “Partial” or “Slumber” state – when it isn’t being used.
If you're looking solely at transfer rates, the USB 3.0 specification – with its 5Gbps speeds – may be plenty fast, but it already can't push the same amount of raw data as, say, Thunderbolt. New specifications coming down the pipeline, like SATA Express and external PCIe, are promising speeds that flat-out blow USB 3.0 out of the water. The USB Promoter Group's aiming to stay in the race with an innovative tactic; rather than compete solely with transfer rates, they're also turning the familiar USB connection into the equivalent of a 100W power cord.
If you're talking music, mashups are so, like, 2005. To be honest, we never really got into mixing Disturbed with the Backstreet Boys to begin with. But when you start talking data transfer specification mashups our ears start to perk up. Our sonic receptors are standing at full attention today, after the Serial ATA International Organization announced the development of a new specification that combines the SATA infrastructure with the PCIe interface to form a Voltron-like super-spec.
Move over USB, because PCI Express is going 3.0, too. PCI-SIG, the special interest group responsible for PCI Express, published the PCI-E 3.0 specification on Thursday, which the consortium describes as a low-cost, higher-performance I/O technology that now includes a new 128b/130b encoding scheme and a data rate of 8 gigatransfers per second. In other words, double the bandwidth of PCI-E 2.0.
"Each new version of the PCI-E spec has doubled the bandwidth of the prior generation," said Nathan Brookwood, research fellow at Insight 64. "The latest group of PCI-E architects and designers drove the standard forward while maintaining complete backward compatibility for Gen 1 and Gen 2 devices. Rarely has a standard advanced so non-disruptively through three major evolutionary cycles. The ability to pull this off demonstrates not only the ingenuity of the Gen 3 developers, but also the insight of those who defined the earlier versions in such an extensible manner."
Want more numbers? The PCI-SIG says products designed for PCI-E 3.0 can "achieve bandwidth near 1GB/s in one direction on a single-lane (x1) configuration and scale to an aggregate approaching 32GB/s on a sixteen-lane (x16) configuration." What the new encoding scheme does is allow for near 100 percent efficiency, PCI-SIG says.