Sometimes, crystal balls are made of silicon. To glimpse the future, look at extreme microprocessor designs, even if you’ll never buy one. In this case, trickle-down theory really works.
Consider Fujitsu’s new SPARC64 X, the company’s tenth-generation implementation of the SPARC architecture. Never heard of SPARC? Don’t feel bad. Although it was a pioneering RISC architecture, now it is clinging to life.
SPARC was introduced in the 1980s by Sun Microsystems, which Oracle acquired in 2010. Fujitsu and Oracle are the only major SPARC vendors, and their processors are found mainly in their own servers and supercomputers. One of Fujitsu’s supercomputers has 88,128 SPARC chips and was recently the world’s fastest.
SPARC64 X has 16 dual-threaded cores, 24MB of cache, and is targeting 3GHz. Only the core count beats Intel’s Xeon server processors, but the usual specs aren’t what grabbed my attention. It was the numerous error-checking circuits—thousands of them.
All server processors support error-correction codes (ECC) on their memory interfaces to verify data reads and writes. Some processors also have ECC or parity protection on their caches and registers. Only a few processors provide error protection for their internal data pathways, peripheral-I/O interfaces, and other critical components.
SPARC64 X does all that and more. It blankets almost the entire chip with 53,000 error-checking circuits. Among other things, they can trigger an automatic instruction-retry mechanism if something goes wrong. Without any software intervention, the chip can re-execute a program instruction that was derailed by a transient soft error. These errors can be caused by electromagnetic interference or even cosmic rays, and they are becoming more common as transistors keep shrinking.
Not every microprocessor needs this extreme level of error protection right now, but my crystal ball tells me that someday, they will.
Note: This column was from the December 2012 issue of the magazine.