By now you’ve probably heard about Intel’s new QuickPath Interconnect, briefly known as the Common System Interface (CSI). QuickPath is Intel’s answer to HyperTransport, the high-speed point-to-point serial interface that AMD adopted years ago. HyperTransport connects the processor core to the on-chip memory controller. On AMD’s multicore chips, HyperTransport also connects the processor cores together.
Thanks partly to HyperTransport, AMD’s processors have enjoyed advantages in memory performance, system integration, and power consumption. Now Intel is overcoming those advantages. New Intel micro-architectures like Nehalem are faster and more efficient, and QuickPath will match or exceed the performance of HyperTransport. QuickPath will appear in future Intel CPUs based on Nehalem.
However, QuickPath serves another purpose: It gives Intel an additional way to differentiate its x86 microprocessors from each other. These differences will be subtle but could measurably affect performance.
The oldest way to differentiate microprocessors within a product line is to offer them at various clock frequencies. All else being equal, higher speeds are better. Another differentiation that became common in the 1990s is to offer different-size caches. All else being equal, bigger caches are better.
More recently, yet another differentiation is to offer multiple processor cores. All else being equal—and assuming that multicore software is available—the more cores, the better. Ideally, those cores are integrated on a single die. Or multiple dies can be united in a single package.
Nehalem-based CPUs will differentiate in all those ways, but also in another: the configuration of their QuickPath connections. Consider the possibilities for a quad-core CPU. A lower-cost, lower-performance version could link the four cores together in a simple square. Each core could communicate with its two neighbors in one hop, but cores at opposite corners would require two hops.
Now picture a square configuration crossed with an “X” in the middle. These extra QuickPath connections would give each core a one-hop connection to every other core. This design is more expensive but delivers greater performance.
Of course, AMD can do the same with HyperTransport. The point is that future multicore chips will differentiate themselves by their interconnects, as well as by the usual factors. Two multicore CPUs with identical clock speeds, caches, cores, and integrated features may perform quite differently, depending on the arrangement of their internal pathways.
Tom Halfhill was formerly a senior editor for Byte magazine and is now an analyst for Microprocessor Report .