Crucial’s DDR4 Memory Out By December

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devin3627

read "Hey.That_Dude"'s post. this article only explains the tip of the iceburg. there's much more about DDR4 that should be understood. i used two DDRs since DDR1. DDR4 is much more than we know previously by older knowledge.

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Hey.That_Dude

OKAY! Just to be clear, with certain people running around trying to guess about DDR4.
Here is a whole article about how DDR4 is using it's data rate and how everything works with data transfers
http://www.synopsys.com/Company/Publications/DWTB/Pages/dwtb-ddr4-bank-groups-2013Q2.aspx
Spoiler: Everything is still 64-bit (because so are our processors).
My captcha for this post is: ynZva

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devin3627

thank you. this really explains in-depth. wikipedia was too generic and broad with its detail.

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devin3627

im a super big loss here guys!! DDR3 wiki mentions 64-bit per ram stick. but is DDR4 64-bit per chip or 128-bit, or an entire different techlogy in general. do we know yet?!?! how does mult-channel work on ddr4? its not clear and im not seeing any information since it'd seem 64-bit ddr4 would bottleneck with 64-bit address space? we need to be informed as users how this works with new technology.

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Hey.That_Dude

I'm metaphysically viewing you a chicken with it's head cut off. Take a chill pill Devin. Ask yourself these questions: Am I an Electrical Engineer? Do I have years of experience looking at timing diagrams? Can I read a Technical Data Sheet and understand what the hell is going on?

If you couldn't answer yes to the last one, then calm down and trust that the engineers involved know that they need to make a truly faster product for people to adopt it (and for them to keep their jobs). If you answered yes to the last one, ask JEDEC for a copy of the data sheet.
Or you could do what everyone else does and hope that Wikipedia is correct.
"...where parallelism was moved from the interface to the controller"
You can no longer look at this like a "DDR3" module. You will interpret the data incorrectly. There is no parallelism in the DDR4 standard. If you want to know what the individual chip's capabilities are then go ask Hynix or another DDR4 maker.

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devin3627

so im going to be dropping from 128-bit to 64-bit ddr4 that decides to not support multi-channel to double speeds. this technology sucks, its a downgrade from ddr3 because the address width is 64-bit ans theres no way for dualchannel anymore for ddr4.

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Hey.That_Dude

It's going to use a point to point architecture. They are generally better in high speed data buses. Please note that this means there is NO DIRECT COMPARISON TO HOW THE DATA IS TRANSMITTED WHICH MEANS STOP FREAKING OUT ABOUT THE BIT WIDTH! The bit width is going to completely depend on the memory controller and isn't specified inside of the DDR4 standard. More than likely it AMD and Intel and everyone else will make it into a 128 bit or 256 bit arch.
In addition there is still the option of switched data banks and "Through-via" stacked chips that should blow DDR3 out of the water.

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MAIZE1951

Wait, why are we not going straight to DDR5 as the majority of video cards have it already, or must we use DDR4 first?

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praetor_alpha

Video cards don't have DDR5. They have GDDR5, which is a GPU optimized version of DDR3 (confusing, I know). It's specialized for graphics and supplies more bandwidth.

https://en.wikipedia.org/wiki/GDDR5

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Cy-Kill

GDDR & DDR are basically two different memory types, so while GDDR is now 5, DDR is only going to 4.

There should be someone on here who can explain it in more detail.

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aarcane

How does doubling the capacity from 8GiB to 16GiB result in a 300% increase?

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Thiazolium

If you look at the diagram it states density goes from 1Gb to 4Gb for DDR3 to DDR4 respectively. Also, the corresponding histogram echoes the same increases.

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vrmlbasic

Wow. DDR3 stuck around a LONG while. It is almost the "Xbox 360" of RAM standards. Hopefully AMD will get its memory controller in gear by then. Also hoping that this will inspire AMD to make a new non-APU "enthusiast" chipset, something they haven't done in 2+ years.

When will the deluge of "No point in going faster than 1333Mhz because benchmarks say your processor is already slower than the memory" comments show up here?

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Hey.That_Dude

It's already been proven that faster RAM helps with on board graphics. So the ones who do say "No point going faster" aren't quite paying attention.

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Renegade Knight

Now I have a target for my next gaming machine upgrade.

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praetor_alpha

It would be nice if PC chipsets/CPUs that supported it were out at the same time, too.

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Hey.That_Dude

Haswell-E is supposed to support it. Not too long of a wait.

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Gikero

Both of my main systems are C2D with DDR2 RAM. Going to DDR4 will be quite the jump. xD

Wondering if the LP version of DDR4 will be around 1V. Maybe DDR4 will be so power efficient that there isn't a official low power spec?

Up to 16GB DIMMs? I expected higher capacities. Don't current DDR3 DIMMs cap at 8GBs? Maybe that is all that is physically possible right now? Granted, 4 X 16GB in a normal system would be insane.

Looking forward to seeing it in a system!

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devin3627

does anyone know if ddr4 is 128-bit vs 64-bit ddr2 or ddr3? that would be awesome if one stick of ddr4 could out-perform two ddr2 sticks. it'd be sweet if you could get 256-bit ddr with two sticks, otherwise 4-DDR3's do quad-channel to achieve a 256-bit pipeline.

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John Pombrio

The DDR4 wiki just mentions a few more connections to address the increased, errr, address.

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devin3627

someone correct me. "In addition, there are 3 chip select signals (C0, C1, C2), allowing up to 8 stacked chips to be placed inside a single DRAM package. These effectively act as three more bank select bits, bringing the total to 7 (128 possible banks)." -wikipedia, dies "128 possible banks" mean 128-bit bus vs ddr3's 64-bit bus? clear words here.

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Hey.That_Dude

How many bytes in a Bank? One? Two? Eight?

Stop guessing. We'll find out when(if) it get's here.

Edit:
Through the use of the internet: a Bank is a group of 2, 8n pre-fetch modules that talk to the memory arrays they control respectively.