Intel generated a lot of press with the unveiling of their 3D, low-power Tri-Gate transistor technology. Now it's IBM’s turn to hop into the 3D waters. Today, the company announced that it’s entered into a joint partnership with 3M to develop 3D semiconductors. They’re going about things a little bit differently than Intel, though; rather than developing chips with raised elements, IBM and 3M want to create “bricks” out of up to 100 separate silicon chips in a process known as “3D packaging.”
The press release says that theoretically, the technology could develop a silicon “brick” that brings memory, networking and processors together in a super-charged chip capable of performing 1,000 times faster than the speediest processors on the market today. That’s all conjecture and theory, of course, but it’s nice to know they’re thinking big.
The key to 3D packaging lies in adhering chips to one another with glue that is capable of transferring heat without damaging logic circuitry. That’s where 3M comes in. The company will be tasked with developing an adhesive that can meet those strict requirements as well as be applied to hundreds or thousands of chips at once. Current 3D packaging involves stacking chips one-by-one, a time-consuming procedure. IBM, on the other hand, will focus more on creating new 3D packaging processes capable of stacking hundreds of silicon wafers at once.
It is, and always has been, a heat issue. All the transistors deep in a stack of silicon have no place to dissipate the heat. Transferring it up layer by layer is OK but, like elevators, it takes up room that could have silicon in it instead. This has been tried many, many, many times over the years but always has proved impracticable.
This seems like in would either be quite wasteful of electricity or be quite a bus hog with communication, seeing as how the top chip would have to still send signal down through the rest to the motherboard.
your kidding me right, think outside the box. this would be awsome, and revolutionary. with layers, the nmber of transistors that can be put on a single chip just goes up, and by alot. The brick idea is just to put all the components that use/need the cpu directly inside of it. everything but the hdd or ssd, ram, and gpu could go there, and yea, the performance would be insane. there is also an article where they said there doing the same thing with ram modules, by stacking the ram chips themself on each other. i dont know why you would say it would waste electricity, when it would do the oposite. the shorter the distance to each component the better, and when they are litterally on top of one another its almost instant.
the only thing a motherboard does is connect the hardware components together
each chip on the mobo comunicates with the cpu, so why not build the chips into the cpu itself...
I guess my thinking is more of the original Pentium Dual-cores, where they had to share the FSB to communicate; this seems like it would be similar, since anything intended for a processor at the top of the stack would have to pass through all the ones on the bottom, and any signal sent from the top would have to travel back to the bottom. Though I'll be the first to admit that I'm not a silicon engineer, so my thoughts may be moot.
But could you imagine the cooler on this thing? You would need a 2 foot thick case.
this is far from being real because i can feel so much wrong. heating and bus use, but if they make the nano size super small, then they can widden the transistors and stack.
I'll just point out that you don't necessarily need to go top down on the bus. There's nothing saying you can't go out the the sides (or even the top of the chip) and the socket doesn't have to be flat.
You can't "3D print" a chip, because 3D printing is used to manufacture things only based on outer form and perhaps very simple inner cavities (i.e. a cup, a box, a pipe). You can't laser silicon on a distinct layer on the interior of a 3D "brick," because obviously the outer sides would block lasers. The only way to mass produce any kind of "3D chip" with today's technology is to layer specially designed (but still relatively conventional in terms of circuits and hardware) microprocessors that are meant to have (also specially designed) vertical interconnects.
You seem to be confused as to how is 3D printing works.
For one, as an additive manufacturing process, there is no single method for printing.
I have actually made a crude chip model (it was a proof of concept thing) using FDM (Fused Deposition Modeling). I had to actually use two machines to switch between metal and the thermoplastic (which I could do since I was only printing a single layer), but this is something that can be fixed by using more printer heads/nozzles. The 3D packaging that IBM is talking about is very similar to the lamination method of 3D printing.
However what I find as the e most likely method to be used is 3D inkjet printing as it is one of the best methods of 3D microfabrication currently available, though the field is still young.
What I think you are most confused about is that 3D printing can't do complex cavities, I can tell you it most certainly can. It called support material, often some thermoplastic, which is deposited or layered where ever a cavity would be. After the printing process (or during certain parts of it, if they are interior cavities that will be enclosed) the support material is dissolved. There is no shape that can't be printed with 3D printing; the only questions are of scale and the variety of materials used in the printing.
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