EVGA Releases New Details on Upcoming 7 Series Motherboard

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TheMiddleman

Hmm.. no internal USB 3.0 header a huge fail in my book. What do you want to bet that one of those pairs of SATA III ports is attached to a Marvell controller, just like current gen Z68 boards?

I almost held out for Ivy Bridge because I thought both sets of 6gbps ports would be intel controlled, but all the previews I've seen of Series 7 boards look to be no different than my Asus P8Z68 in this regard.

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JohnP

I will trade you EVGA's Thunderbolt for ASUS's built in WiFi.

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acidic

here is a much better preview of a retail 7 series chipset

http://www.guru3d.com/article/asus-sabertooth-z77-preview/1

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t.y.wan

2x 8pin at the top, 1x 6pin just above the pci-essss and 1x more at the bottom left hand side. Looks super power hungry!
But then, there ain't no chipset heatsink, suggesting a extremely low idle power usage?

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whr4usa

is there any real technical reason for boards having SATA II & III, and USB 2.0 & 3.0 sXs on the same board from the same chipset when they're fully backwards compatible..? is this just lame chipset design trying to save power, space, design time by conserving PCIe lanes\bandwidth..? can MaxPC shed some light on this..?

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Hey.That_Dude

This is an attempt to save bandwidth only. If you look at how many USB2==USB3 (10==1) then you start to understand. You'll also note that NO ONE is pushing 10G internet even though they have chips that can push it without generating too much heat. Why? same issue (10==1) bandwidth issues. As for the sata ports... they're just lazy.
The bandwidth issue is also related to the Lithography used the produce the controller hubs (~60 nm). To get full bandwidth on USB 3.0, SATA R.3, and PCIe 3.0 they need to hit something more like a (~40 nm) scale... Since some of these companies are still using 40 nm to make some of their CPU products (AMD) this won't happen for a while. (eg. about 1-2 years).

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whr4usa

limited PCIe lanes ftw.

yeah processors on 32nm, intel pch on 45nm, most other hubs\controllers @ 65nm . . . didn't realize potential bandwidth capcity was related to lithogrpahy like that other than for scalability within a given formfactor

ethernet doesn't consume motherboard resources in direct relation to network bandwidth and usualy isn't an integral par of the PCH but I still take your point sir!

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Hey.That_Dude

Not just chip space related. Granted that the additional space would help pack more features and lanes, however efficiency is key. The 60nm lithography produces a serious amount of heat when compared to 40nm. this means that I'd need approximately 1.5x more cooling, 1.5x more space to cool off in, more complexity, high silicon usage thus higher chip cost,... list goes on.

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whr4usa

Oh I'm well aware of that ...bit of a hardware guru here myself too! just never have found any documentation et al. on bandwidth being directly related and indirectly derived from lithography but now that you've turned me onto that line of thinknig it actually makes a lot of sense, especially if you look at it from the networking perspective [photons v. electrons]

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