AMD's newly appointed CTO Mark Papermaster provided the public with its first glimpse of its upcoming Steamroller x86 CPU core. Steamroller represents the third generation of AMD's Bulldozer architecture, succeeding Piledriver (second generation) with improved parallelism, increased performance, and more instruction cache, which will lead to 30 percent fewer cache misses and a 20 percent reduction in mistaken branch predictions.
If you recall, Piledriver was more about power efficiency than it was improving performance. Steamroller, while based on the same architecture, includes several tweaks to address the latter, including larger L1 cache. This time around, AMD is doing away with the shared fetch and decode strategy inherent in Bulldozer, which limited the architecture to being able to decode just four instructions per processor, and introduces a dedicated decode for each integer pipe. This is a big deal, as Bulldozer topped out at 16 decodes in a four module, eight-core CPU, whereas Sandy Bridge and Ivy Bridge both boast 4 instructions per core, adding up to 32 decodes per eight-core CPU.
The changes Streamroller brings to the CPU scene probably won't be enough to compete with Ivy Bridge, but it's a definite step in the right direction (on paper, anyway). AMD says Steamroller will ship in 2013. In the meantime, HotHardware and Anandtech both have posted in-depth breakdowns of the platform with a handful of AMD slides to digest.