AMD Announces Phenom II X4 and Promises Move to 32nm by 2011

Alex Castle

AMD will dub the 45nm die shrink of its consumer enthusiast CPU as Phenom II X4 and laid out plans for its first CPUs with integrated graphics core.

The Phenom II X4 is on tap for late this year and will follow the company’s smaller, faster 45nm Opteron chips. The new chip will feature 8MB of cache and support both DDR2 and DDR3 in the AM3 and AM2+ sockets. Phenom II X4 will be part of AMD’s “Dragon” platform that combines the new chip with DX10.1 graphics, the company’s new Stream GPU processing, OverDrive and Fusion for gaming utility.

The first PII X4 won't be available until early next year which drew questions of AMD's committment to power users. Company officials responded that AMD still cares about power users but it wasn't going to "wring its hands" over not having a competitor to Core i7 in time for Christmas. The company said that while power users are important, the company is more concerned with the main stream market where the lion's share of its profits come from. AMD didn't comment on performance but its expected to at least mirror the server-version of the chip. AMD said its 45nm server chip will offer 35 percent more performance than its existing chips with no additional power cost. Those chips are expected to ship in the 2.3GHz to 2.7GHz range.

AMD also announced plans for a 32nm family of chips as early as 2011. On the top end, a quad-core Orochi with 8MB of cache and DDR3 will hopefully keep enthusiasts happy. Orochi is part of AMD’s Bulldozer family that mysteriously disappeared from the company’s roadmap earlier this year. Until Orochi is available, the 45nm Phenom II X4, previously codenamed Deneb  will hopefully fight off Intel’s Core i7 chips.

The move to 32nm will also see the Llano chip. The CPU will feature four cores, 4MB of cache, DDR3 and an integrated graphics core. AMD, meanwhile, confirmed it would be taking on Intel’s Atom chip with its Conesus CPU next year. Conesus will be dual-core, feature 1MB of cache and DDR2. In 2010, Conesus will give way to Geneva which doubles the cache to 2MB.

Updated with timing of Phenom II and performance questions.

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